1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having an error correcting circuit (ECC).
2. Description of the Related Art
Among recent semiconductor memories and, for example, dynamic random access memories (DRAMs), semiconductor memories having an error correcting circuit using an error correcting code, e.g., a Hamming code are becoming popular.
In a semiconductor memory with an ECC function, at the time of, e.g., a write operation, parity bits are generated from write data. The write data is written in memory cells as information bits. The parity bits are also written in memory cells.
In a read operation, the parity bits are read out from the memory cells together with the information bits. A syndrome signal is generated from the readout information bits and parity bits. The syndrome signal is input to an error detection circuit. The error detection circuit detects on the basis of the syndrome signal whether the information bits have errors. When an error is detected, an error correcting circuit corrects the information bit error on the basis of the output from the error detection circuit. After the correction, the information bits are output as read data.
In data read out from the memory cells in the initial state and, for example, data read out from the memory cells upon power-on (or immediately after power-on), both the information bits and the parity bits are not always correct code words. In, e.g., a dynamic RAM, charges stored in the memory cells are discharged after power-off. After power-off, data in all memory cells are data corresponding to “no charges”, e.g., data “0” at a high probability. When all data read out from the memory cells at the time of power-on are all “0s” (or all “1s”), both the information bits and the parity bits are not always correct code words. As a result, a correct information bit may be corrected on the basis of a wrong parity bit.
Known examples of a semiconductor memory with an ECC are as follows.                1. Japanese Patent No. 2642094        2. Jpn. Pat. Appln. KOKOKU Publication No. 6-85280        3. Jpn. Pat. Appln. KOKAI Publication No. 5-217398        4. Jpn. Pat. Appln. KOKAI Publication No. 1-183000        5. Jpn. Pat. Appln. KOKAI Publication No. 2003-85996        6. Jpn. Pat. Appln. KOKAI Publication No. 8-195099        7. Jpn. Pat. Appln. KOKAI Publication No. 7-220495        8. U.S. Pat. No. 6,490,703        